Thin-film magnetic random access memories (MRAM) are of interest because of their potential application to nonvolatile and volatile memories. In a conventional MRAM, the magnetic storage cell typically includes a magnetic tunneling junction (MTJ) stack having a free layer, an insulating tunneling barrier layer, and a pinned layer. Use of a conventional MTJ stack makes it possible to design an MRAM cell with high integration density, high speed, low read power, and soft error rate (SER) immunity.
A conventional MRAM also includes bit lines and word lines, which are generally orthogonal. Note that the names of the conventional conductive lines are interchangeable. Other names, such as row line, column line, digit line, and data line, may also be used. The magnetic storage cells are typically located at the intersections of bit lines and word lines. In order to program a particular magnetic storage cell, write currents are driven through both the word line and the bit line associated with a particular magnetic storage cell. A current in only one of the word line or bit line is insufficient to write to the cell. However, in combination, the current provide a sufficient magnetic field to program the MTJ stack as desired.
Although such a conventional MRAM functions, one of ordinary skill in the art will readily recognize that such a conventional MRAM may inadvertently write to nearby cells. Consequently, conventional word lines may be segmented. In such a conventional MRAM, a conventional global word line is coupled through a switch, such as a transistor, to each word line segment. A number of magnetic storage cells, and thus a number of bits, are associated with each segment. As discussed above, a bit line is orthogonal to the segment at each magnetic storage cell. Typically, eight or sixteen bits are associated with each segment in a conventional MRAM having segmented word lines. In a conventional MRAM having segmented word lines, a programming current is provided only to a particular segment of the word line during writing. As a result, the possibility of inadvertently writing to cells not associated with the segment is substantially reduced.
For example, FIG. 1 depicts a conventional method 10 for writing to magnetic storage cells associated with a particular segment. A conventional write current, I1, is provided to the word line segment, via step 12. In general, step 12 is performed by turning on the transistor associated with the word line segment so that current flowing through a global word line flows through the selected word line segment. Thus, the remaining word line segments do not carry a current, reducing the possibility that MTJ stacks associated with these word line segments will be inadvertently written. A second write current, I2, is provided to the conventional bit lines associated with the word line segment being programmed, via step 14. The combination of the currents in the word line and bit line are sufficient to program the desired magnetic storage cells associated with the word line.
Although the above conventional MTJ stack can be written using the conventional method 10, one of ordinary skill in the art will readily recognize that use of the segmented word lines results in a large overhead for the conventional MRAM. FIG. 2 depicts an asteroid chart 50 for MTJ stacks in a conventional MRAM. The margin to ensure programming of bits within the conventional MRAM is shown as IM. The safety margin within which other magnetic storage cells along the bit line will not be disturbed is shown as IS. In general, the current in the word line segment, I1, provided in step 12 is at point a in the chart 50. The current provided in the bit line, I2, in step 14 is shown at either point b or point c in the chart 50. Because of this biasing, it is still possible that other memory cells associated with the same word line segment are inadvertently written in the conventional method 10. In order to reduce this possibility, the number of magnetic storage cells associated with a particular word line segment is small. As discussed above, therefore, conventional MRAM are typically organized based on eight bits or sixteen bits. Thus, when a write operation is performed using the method 10, all the bits associated with a particular word line segment are written in step 14. The MRAM uses a selection transistor for each word line segment. The size of the transistor used in selecting the word line segment is a significant overhead for the number of bits (eight or sixteen) associated with a word line segment. Consequently, there are still significant drawbacks to the use of a conventional MRAM utilizing conventional segmented word lines.
Accordingly, what is needed is a system and method for providing a lower overhead MRAM that is less likely to inadvertently write to nearby magnetic storage cells. The present invention addresses such a need.